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Design Verification Engineer

Verify thermodynamic ASICs from design to tapeout using testbenches and assertions

As a Design Verification Engineer at Normal, you will own design verification for the company's physics-inspired ASICs, including creating testbench environments, writing assertions, and achieving functional coverage from design documents through to tapeout. You will also review AI-generated verification collateral to refine product strategy and set the quality bar for training data used by machine learning models. Additionally, you may suppor...

Why This Role?

Work on physics-inspired ASICs that compute with thermal noise for 10-100× more AI inference per dollar and watt

Key Responsibilities

  • Own design verification for Normal's internal thermodynamic ASICs from design documents to tapeout
  • Create and maintain testbench environments, assertions, and coverage models for functional verification
  • Review AI-generated verification collateral to shape product strategy and tool usability with ML and product teams
  • Define rubrics and curate golden examples to set the data quality bar for verification training data
  • Support customer deployments by validating AI-generated collateral against real customer specifications
  • Collaborate with forward-deployed and data teams to ensure AI learns from verification artifacts a real DV engineer would sign off on

Requirements

  • Experience in design verification for ASICs, including testbench development and assertion-based verification
  • Knowledge of functional coverage and closure processes in DV flows
  • Familiarity with reviewing verification collateral and setting quality standards for training data
  • Ability to collaborate with ML, product, and data teams on AI-driven verification refinement
  • Experience supporting customer engagements in a verification or deployment support role

Required Skills

asic-verificationtestbenchassertionsaidata-qualityDesign VerificationTestbench DevelopmentAssertion-Based VerificationFunctional CoverageASIC VerificationAI-Generated Collateral Review
View Original Description from Ashby Job Boards

Original description from Ashby Job Boards

ABOUT NORMAL COMPUTING Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt. We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing. Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority. THE ROLE As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat. WHAT YOU WILL OWN - Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout. - AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams. - Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on. - Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments. - Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments. WHAT MAKES YOU A GREAT FIT - 5+ years of experience in digital verification at a major semiconductor or EDA tool company - Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting - Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction - Willingness to occasionally support customer-facing deployment work, including some travel - Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session BONUS POINTS - Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company - Hands-on use of LLMs or agentic tools in verification workflows - Exposure to analog, mixed-signal, or unconventional compute verification Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Salary Context

Similar Design roles on LokerDollar pay around $169k/yr (range $7.2k–280k/yr, n=93 active listings).

Hiring at Normal

Normal has 15 other active roles on LokerDollar and has been hiring here since Aug 3, 2026 — across Design, Data & Analytics, Engineering.

View all Normal openings →

Openness not stated by employer — check the listing

Company
Normal
Estimated salary
$140k–170k/yr
Based on similar roles — not stated by the employer
Job Type
full time
Location
null · Remote
Category
Seniority
mid
PostedRecheck the source
Jul 15, 2026

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Frequently asked questions

Is Design Verification Engineer at Normal a remote job?
This role is based in Remote. See the listing for remote/onsite details.
What type of employment is Design Verification Engineer at Normal?
This is a full time position.
How do I apply?
Click the "Apply" button on this page to go to the official application at Normal.

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