Hardware Engineer, RTL
Desain dan verifikasi logika digital untuk perangkat keras termodinamika
Sebagai RTL Design Engineer di Normal, Anda akan mendesain dan memverifikasi logika digital di inti perangkat keras termodinamika. Anda akan menulis spesifikasi mikroarkitektur, membuat SystemVerilog yang dapat disintesis, dan bekerja sama dengan tim verifikasi dan desain fisik untuk memastikan desain memenuhi batasan area dan waktu. Normal bekerja dengan tim satu di berbagai lokasi, termasuk New York, Silicon Valley, London, Copenhagen, dan Seou
Kenapa Menarik?
Dapatkan kesempatan mengembangkan RTL menggunakan SystemVerilog untuk chip AI yang efisien hingga 100x lebih baik per dolar dan watt.
Tanggung Jawab Utama
- Menulis dan memiliki RTL yang dapat disintesis dalam SystemVerilog untuk berbagai blok logika
- Mengubah spesifikasi tingkat tinggi menjadi mikroarkitektur yang dapat diimplementasikan
- Bekerja sama dengan tim verifikasi untuk merencanakan verifikasi, membantu debug, dan menutup koverasi
- Bekerja sama dengan tim desain fisik untuk memastikan desain memenuhi batasan area dan waktu
Persyaratan
- Pengalaman dalam desain RTL dan SystemVerilog
- Pengalaman dalam verifikasi desain dan penutupan koverasi
- Kemampuan untuk bekerja sama dengan tim arsitektur, verifikasi, dan desain fisik
- Pengalaman dalam mengetes dan memverifikasi desain silikon
Skills Wajib
Lihat Deskripsi Asli dari Ashby Job Boards
Deskripsi asli dari Ashby Job Boards
ABOUT NORMAL COMPUTING Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt. We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing. Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority. THE ROLE As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence. You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it. This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel. WHAT YOU WILL OWN - RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces. - Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures. - Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage. - Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT. - Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation. - Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed. WHAT MAKES YOU A GREAT FIT - Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route - Experience in closing coverage to a high level - At least one tapeout in your background, from any node and any company size - Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront - Strong debugging instincts across simulation, waveforms, and formal counterexamples - Ability to work directly with architects and physical designers without needing a large intermediary layer - Industry experience in ASIC or SoC design BONUS POINTS - Experience at an AI chip company where design and verification were tightly coupled - Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 - Familiarity with RISC-V or other open ISAs - Experience with AI-assisted RTL or EDA tooling in your design workflow - Exposure to physical design constraints, floorplanning, or timing-driven RTL development Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Konteks Gaji
Posisi Engineering serupa di LokerDollar dibayar sekitar $170k/yr (kisaran $855–1000k/yr, dari 709 listing aktif).
Perekrutan di Normal
Normal punya 16 lowongan aktif lain di LokerDollar dan telah merekrut di sini sejak 3 Agu 2026 — di kategori Engineering, Data & Analytics.
Lihat semua lowongan Normal →Pemberi kerja tidak menyatakan keterbukaan lokasi — cek langsung lowongannya
Pertanyaan yang sering diajukan
- Apakah Hardware Engineer, RTL di Normal bisa dikerjakan remote?
- Posisi ini berlokasi di Remote. Detail remote/onsite ada di deskripsi lowongan.
- Berapa gaji untuk Hardware Engineer, RTL di Normal?
- Rentang gaji yang tercantum untuk posisi ini adalah $200k–400k/yr.
- Jenis pekerjaan apa Hardware Engineer, RTL di Normal?
- Posisi ini adalah pekerjaan full time.
- Bagaimana cara melamar?
- Klik tombol "Lamar" pada halaman ini untuk menuju halaman aplikasi resmi Normal.
Jelajahi lebih lanjut
Data & laporan pasar
Riset gaji & permintaan skill dari data lowongan kami sendiri.
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- Remote ≠ Remote: Skill yang Membuka Kerja Global untuk Indonesia (2026)12.891 lowongan remote: skill coding bergaji tertinggi justru paling terkunci untuk pelamar Indonesia. Dataset agregat CC BY 4.0.
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- Benchmark Gaji IndonesiaKisaran gaji agregat lintas peran, dengan metodologi dan dataset terbuka.
- Indeks Gaji & Permintaan Kerja Remote untuk IndonesiaBerapa banyak lowongan remote global yang terbuka untuk Indonesia, dan gajinya (USD) per bidang.
- Laporan Kuartalan Pasar Kerja IndonesiaPHK, pendanaan, gaji & skill per kuartal — agregat terbuka.
- Laporan Pasar Remote per PeranLaporan otomatis per kelompok peran — skill, senioritas, perusahaan, gaji.
- Benchmark Gaji Remote GlobalGaji tahunan per bidang & mata uang, plus porsi lowongan terbuka untuk seluruh dunia.
Dari blog kami
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